In recent years, SiC has attracted attention as a material for a power device having high electric field breakdown strength. A SiC semiconductor device can control a large electric current due to its high electric field breakdown strength. Therefore, the SiC semiconductor device is expected to be used to control a motor of a hybrid vehicle.
Increasing channel density is an effective way to allow a larger electric current to flow in a SiC semiconductor device. Therefore, in a silicon transistor, a MOSFET having a trench-gate structure has been adopted and put to practical use. A trench-gate structure can be applied to a SiC semiconductor. However, there is a big problem, when the trench-gate structure is applied to SiC. That is, since electric field breakdown strength of SiC is ten times greater than that of silicon, a voltage applied to a SiC semiconductor device during use is approximately ten times greater than a voltage applied to a silicon device during use. Therefore, a voltage applied to a gate insulating film formed in a trench in SIC is approximately ten times greater than a voltage applied to a gate insulating film formed in a silicon device. As a result, it is likely that a breakdown of the gate insulating film occurs at a corner of the trench. A result of a simulation regarding this indicates that when a voltage of 650V is applied to a drain, an electric field of 4.9 MV/cm acts on a gate insulating film in a trench. For practical use, the electric field needs to be equal to or less than of 3 MV/cm. When taking into consideration long-term reliability, it is preferable that the electric field be equal to or less than of 2 MV/cm.
U.S. Pat. No. 6,133,587 (JP-A-H9-199724) discloses a SiC semiconductor device designed to solve the above problem. In this SiC semiconductor device, the thickness of a bottom wall of a trench is made greater than the thickness of a side wall of the trench to relieve electric field concentration on the bottom wall of the trench. Specifically, a a-face (1120) trench gate structure is formed by using a c-face (000-1) substrate of 4H-SiC. That is, a trench having a a-face side wall and a c-face bottom wall is formed by using the c-face substrate. When a gate insulating layer is formed in the trench by thermal oxidation, an oxidation rate of the c-face is five times greater than that of the a-face. Accordingly, the thickness of the gate insulating layer in the trench becomes five times greater on the trench bottom wall than on the trench side wall. Therefore, the electric field concentration on the trench bottom wall can be reduced.
In a simulation, the thickness of the gate insulating layer on the trench side wall is set to 40 nm, the thickness of the gate insulating layer on the trench bottom wall is set to 200 nm, and a voltage of 650V is applied to a drain. The simulation result indicates that the electric field concentration on the gate insulating layer in the trench is reduced to 3.9 MV/cm. However, the reduction in the electric field concentration is insufficient, and a further reduction is required.
The present inventors have filed the patent application (Japanese patent application No. 2007-288545) for a structure for achieving further electric field concentration reduction. The structure has a p-type deep layer that is located opposite side of a trench gate across an n+-type source region and a p-type base region. That is, the p-type deep layer is located under a p+-type contact region that is electrically connected to the p-type base region and a source electrode. The p-type deep layer extends deeper than a bottom wall of the trench gate.
When the SiC semiconductor device having this structure is manufactured, the trench gate and the p-type deep layer are formed by different processes. Since alignment between the trench gate and the p-type deep layer is difficult, there may occur a certain amount of variation in a distance from a side wall of the trench gate to the p-type deep layer. As a result, characteristic variations between products may occur, and yield rates may be low.
The present inventors have filed-another patent application (Japanese patent application No. 2008-31704) for a structure in which a p-type deep layer extends in a direction normal to a potion of a trench side wall where a channel region is formed. In the structure, since a depletion layer greatly extends toward an n−-type drift layer side at a PN junction between the p-type deep layer and the n−-type drift layer, it is less likely that a high voltage due to a drain voltage is applied to a gate oxide layer. Thus, electric field concentration in the gate oxide layer can be reduced, in particular, on the bottom wall of the trench, so that a breakdown of the gate oxide layer can be prevented. In addition, since a longitudinal direction of the trench is not perpendicular to a longitudinal direction of the p-type deep layer, device characteristics are not affected by misalignment between masks used to form the trench and the p-type deep layer.
Further, it has been proposed that an n-type current scattering layer is formed between an n−-type layer and a p-type base layer to further reduce an on-resistance. The n-type current scattering layer allows an electric current passing through the channel region to be widely scattered so that the electric current can flow though the n−-type drift layer. In this way, the on-resistance is further reduced. In such a structure, when a p-type base region and the p-type deep layer are divided by the n-type current scattering layer, the effect of reducing the electric field concentration may be weakened due to the fact that the p-type deep layer is not fixed to a source potential. Therefore, it has been proposed that the p-type layer is formed by performing ion implantation of p-type impurities into a surface of the n-type current scattering layer after the n-type current scattering layer is formed.
However, in a case where the p-type layer is formed by performing ion implantation of p-type impurities into the surface of the n-type current scattering layer after the n-type current scattering layer is formed, the depth of the p-type deep layer becomes small. Accordingly, a difference in depth between a bottom wall of the p-type deep layer and a bottom wall of the trench becomes small so that the effect of reducing the electric field concentration may be reduced. Further, since it is difficult to control the depth of the trench, there is a possibility that the depth of the trench becomes greater than the depth of the p-type deep layer. Since the depth of the p-type deep layer depends on energy of the ion implantation, the depth of the p-type deep layer can be increased by performing the ion implantation at high energy. However, an enormous amount of energy is required to form the p-type deep layer having a desired depth in a solid material such as SiC. Therefore, there is a need to prepare an ion implantation apparatus that can perform ion implantation by using an enormous amount of energy. However, since such an ion implantation apparatus is costly, another approach is required.